PLDs are a well-known type of integrated circuit that may be programmed to perform specified logic functions. One type of PLD, the Field Programmable Gate Array (FPGA), typically includes an array of programmable tiles. These programmable tiles can include, for example, Input/Output Blocks (IOBs), Configurable Logic Blocks (CLBs), dedicated Random Access Memory Blocks (BRAM), multipliers, Digital Signal Processing blocks (DSPs), processors, clock managers, Delay Lock Loops (DLLs), Multi-Gigabit Transceivers (MGTs) and so forth.
Each programmable tile typically includes both programmable interconnect and programmable logic. The programmable interconnect typically includes a large number of interconnect lines of varying lengths interconnected by Programmable Interconnect Points (PIPs). The programmable logic implements the logic of a user design using programmable elements that may include, for example, function generators, registers, arithmetic logic, and so forth.
The programmable interconnect and the programmable logic are typically programmed by loading a stream of configuration data into internal configuration memory cells during a configuration event that defines how the programmable elements are configured. The configuration data may be read from memory (e.g., from an external PROM) or written into the FPGA by an external device. The collective states of the individual memory cells then determine the function of the FPGA.
Another type of PLD is the Complex Programmable Logic Device, or CPLD. A CPLD includes two or more “function blocks” connected together and to input/output (I/O) resources by an interconnect switch matrix. Each function block of the CPLD includes a two-level AND/OR structure similar to those used in Programmable Logic Arrays (PLAs) and Programmable Array Logic (PAL) devices. In CPLDs, configuration data is typically stored on-chip in non-volatile memory. In some CPLDs, configuration data is stored on-chip in non-volatile memory, then downloaded to volatile memory as part of an initial configuration (programming) sequence.
For all of these PLDs, the functionality of the device is controlled by configuration data bits provided to the device for that purpose. The configuration data bits can be stored in volatile memory (e.g., static memory cells, as in FPGAs and some CPLDs), in non-volatile memory (e.g., FLASH memory, as in some CPLDs), or in any other type of memory cell.
Prior to configuring the PLD for operation, a PLD analysis tool may be utilized to analyze the PLD design, whereby implementation constraints may be imposed by the PLD analysis tool to verify the validity of the PLD design. The constraints may be stored within a user constraints file (UCF), or conversely may be specified within the hardware design language (HDL) or synthesis constraints file.
Input interfaces of the PLD design, however, present one of the most problematic and confusing areas for applying timing constraints, due in large part to the proliferation of I/O interface communication standards and their associated specifications. Application of the timing constraints to the input interfaces of the PLDs is especially necessary due to the fact that PLDs are ideally suited for the implementation of a plurality of I/O interfaces that are capable of supporting a large number of I/O interface standards. For example, many PLD based processing systems operate according to the peripheral component interconnect (PCI) standard, which among other features, defines a specification for attaching peripheral devices to a computer mother board. In other examples, PLD based processing systems may also utilize the high speed transceiver logic (HSTL) standard for data transfers to and from memory, and/or the low-voltage differential signaling (LVDS) standard for backplane communications. Other I/O interface definitions continue to emerge as I/O interface standards continue to be developed.
As a result, the PLD designer is plagued with the responsibility of assigning constraints to the various I/O interfaces that support the growing number of I/O interface standards during analysis. In addition, the PLD designer must also account for the specific data rate and data alignment variations that are coupled with the large variety of constraint language options available in order to properly constrain the input interfaces. Still further, the PLD designer is required to have a detailed understanding of the particular constraint language being utilized, so as to create the most efficient and comprehensive set of constraints possible.
Efforts continue, therefore, to simplify the application of input timing constraints to the I/O interfaces of the PLD.